// ------------------------------------------------------------------------

// PAL Video Decoder 

// ------------------------------------------------------------------------

// PAL 601 Toplam 1728 videoClock

// Cb Y Cr Y ...

// ------------------------------------------------------------------------



module VideoDecoder

(

	input	videoInClock,

	input [7:0] videoInData,

	

	output [9:0] Address,

	

	output LumaSample,

	output ChromaSample,

	

	output videoHSync,

	output videoVSync

	

);



// ------------------------------------------------------------------------

// Horizontal Synch Detector 

// ------------------------------------------------------------------------

reg [7:0] sync1;

reg [7:0] sync2;

reg [7:0] sync3;



// ------------------------------------------------------------------------

// Video Input Line Buffer

// ------------------------------------------------------------------------

reg [9:0] regAddress;

reg regChromaSample;

reg regHSync;

reg regVSync;



assign Address=regAddress;

assign ChromaSample=regChromaSample;

assign LumaSample=!regChromaSample;

assign videoHSync=regHSync;

assign videoVSync=regVSync;



always @(posedge videoInClock)

begin

	// HSync Detector

	sync1<=sync2;

	sync2<=sync3;

	sync3<=videoInData;



	// sync4 0b1FVH1234  (1234Protection)

	// H=0 Begin of Video

	// H=1 End Of Video

	if ( (sync1==8'b11111111) && (sync2==8'b00000000) && (sync3==8'b00000000) && ((videoInData&8'b10010000)==8'b10000000) )

	begin

		// Bu clok ile adigimiz son data icerisinde HSYNC isareti var

		// Yani bir sonraki data Cb ile baslayacak, adres 0 olacak ...

		regAddress<=0;

		regChromaSample<=1'b1;

		regHSync<=1'b1;

	end else

	begin

		if (regChromaSample==0) regAddress<=regAddress+1;

		regChromaSample<=!regChromaSample;

		regHSync<=0;

	end



	if ( (sync1==8'b11111111) && (sync2==8'b00000000) && (sync3==8'b00000000) && ((videoInData&8'b10100000)==8'b10100000) )

	begin

		regVSync<=1'b1;

	end else

	begin

		regVSync<=0;

	end

end



endmodule