commodore.gen.tr

// ----------------------------------------------------------------------------
// HDMI64 - C64 Video HDMI Converter (with Scanline Effect)
// [url]www.commodore.gen.tr[/url] - delimawi'2016
// ----------------------------------------------------------------------------
// Project based on HDMI Sample Code from fpga4fun.com
// ----------------------------------------------------------------------------

module HDMI_Converter
(
	input pixelClock,						//  Incomming Video Pixel Clock
	input pixelClockX10,					//  HDMI Bit Clock (pixelClockx10)
	input button,							// Option Button Input
	output [2:0] TMDSp, TMDSn,			// HDMI Output Pins 
	output TMDSp_clock, TMDSn_clock
);

// ----------------------------------------------
// Timing 720x576 @50 Hz
// pixelClock 30MHz
// ---------------------------------------------- 
`define DISPLAY_WIDTH			720
`define DISPLAY_HEIGHT			576
`define FULL_WIDTH				968
`define FULL_HEIGHT				625
`define H_FRONT_PORCH			40
`define H_SYNC					72 
`define V_FRONT_PORCH			3
`define V_SYNC 					28

`define H_SYNC_BEGIN			`DISPLAY_WIDTH+`H_FRONT_PORCH			
`define H_SYNC_END				`H_SYNC_BEGIN+`H_SYNC					
`define V_SYNC_BEGIN			`DISPLAY_HEIGHT+`V_FRONT_PORCH		
`define V_SYNC_END				`V_SYNC_BEGIN+`V_SYNC					

reg [9:0] counterX, counterY;			// 10 Bit X,Y Counters (0-1023)
reg hSync,vSync;						// HDMI Synch Pulses
reg drawArea;							// Drawing Area Flag

always @(posedge pixelClock)
begin
	drawArea<=(counterX<`DISPLAY_WIDTH)&&(counterY<`DISPLAY_HEIGHT);
	hSync <= (counterX>=`H_SYNC_BEGIN)&&(counterX<`H_SYNC_END);
	vSync <= (counterY>=`V_SYNC_BEGIN) && (counterY<`V_SYNC_END);
end
	
always @(posedge pixelClock)
begin
	if (counterX==(`FULL_WIDTH-1)) 
	begin
		if (counterY==(`FULL_HEIGHT-1)) 
		begin
			counterY<=0;
		end else 
		begin
			counterY<=counterY+1;
		end
		counterX<=0;
	end else 
	begin
		counterX<=counterX+1;
	end
end

// ----------------------------------------------------------------------------
// Test Pattern Generator
// ----------------------------------------------------------------------------

reg [23:0]	outColor;	
reg [23:0]	backColor;	
reg [7:0] 	red, green, blue;
reg [7:0] 	redo, greeno, blueo;

always @(posedge pixelClock)
begin
	// Temsili bir C64 bordur görüntüsü yaratalım ...
	backColor=24'h446699;
	if ((counterX>80) && (counterX<640) && (counterY>88) && (counterY<488)) backColor=24'h223377;
	
	// C64 Renk Paletini temsili olarak yerleştirelim ...
	outColor=backColor;

	if ((counterY>150) && (counterY<200-10))
	begin
		if 		((counterX>100) && (counterX<150-10))	outColor=24'h000000;
		else if 	((counterX>150) && (counterX<200-10))	outColor=24'hFFFFFF;
		else if 	((counterX>200) && (counterX<250-10))	outColor=24'h880000;
		else if 	((counterX>250) && (counterX<300-10))	outColor=24'hAAFFEE;
		else if 	((counterX>300) && (counterX<350-10))	outColor=24'hCC44CC;
		else if 	((counterX>350) && (counterX<400-10))	outColor=24'h00CC55;
		else if 	((counterX>400) && (counterX<450-10))	outColor=24'h0000AA;
		else if 	((counterX>450) && (counterX<500-10))	outColor=24'hEEEE77;
	end

	if ((counterY>200) && (counterY<250-10))
	begin
		if 		((counterX>100) && (counterX<150-10))	outColor=24'hDD8855;
		else if 	((counterX>150) && (counterX<200-10))	outColor=24'h664400;
		else if 	((counterX>200) && (counterX<250-10))	outColor=24'hFF7777;
		else if 	((counterX>250) && (counterX<300-10))	outColor=24'h333333;
		else if 	((counterX>300) && (counterX<350-10))	outColor=24'h777777;
		else if 	((counterX>350) && (counterX<400-10))	outColor=24'hAAFF66;
		else if 	((counterX>400) && (counterX<450-10))	outColor=24'h0088FF;
		else if 	((counterX>450) && (counterX<500-10))	outColor=24'hBBBBBB;
	end;

	redo   <= outColor[23:16];
	greeno <= outColor[15:8];
	blueo  <= outColor[7:0];

	// ----------------------------------------------------------------------------
	// Scanline Effect
	// ----------------------------------------------------------------------------
	if (counterY[0]==1)
	begin
	  red <= (redo>>2)*3;
	  green <= (greeno>>2)*3;
	  blue <= (blueo>>2)*3;
	end
	else
	begin
		red<=redo;
		green<=greeno;
		blue<=blueo;
	end
end

// ----------------------------------------------------------------------------
// Generate TDMS Encoded 10 Bit Signals
// ----------------------------------------------------------------------------

wire [9:0] TMDS_red;
wire [9:0] TMDS_green;
wire [9:0] TMDS_blue;

TMDS_encoder encode_R( .clk(pixelClock), .VD(red  ), .CD(2'b00)        , .VDE(drawArea), .TMDS(TMDS_red)    );
TMDS_encoder encode_G( .clk(pixelClock), .VD(green), .CD(2'b00)        , .VDE(drawArea), .TMDS(TMDS_green)  );
TMDS_encoder encode_B( .clk(pixelClock), .VD(blue ), .CD({vSync,hSync}), .VDE(drawArea), .TMDS(TMDS_blue)   );

// ----------------------------------------------------------------------------
// Generate TDMS Clock
// ----------------------------------------------------------------------------

wire clk_TMDS=pixelClockX10;

// ----------------------------------------------------------------------------
// Generate TDMS Signals (Serialise)
// ----------------------------------------------------------------------------

reg [3:0] TMDS_mod10=0;  			// modulus 10 counter
reg [9:0] TMDS_shift_red=0;		// 10 Bit Shift Registers
reg [9:0] TMDS_shift_green=0;		// 10 Bit Shift Registers
reg [9:0] TMDS_shift_blue=0;		// 10 Bit Shift Registers

reg TMDS_shift_load=0;

always @(posedge clk_TMDS) 	TMDS_shift_load <= (TMDS_mod10==4'd9);

always @(posedge clk_TMDS)
begin
	TMDS_shift_red  	<= TMDS_shift_load ? TMDS_red   : TMDS_shift_red  [9:1];
	TMDS_shift_green	<= TMDS_shift_load ? TMDS_green : TMDS_shift_green[9:1];
	TMDS_shift_blue 	<= TMDS_shift_load ? TMDS_blue  : TMDS_shift_blue [9:1];	
	TMDS_mod10			<= (TMDS_mod10==4'd9) ? 4'd0 : TMDS_mod10+4'd1;
end

assign TMDSp[2]    = TMDS_shift_red[0]  ;
assign TMDSp[1]    = TMDS_shift_green[0];
assign TMDSp[0]    = TMDS_shift_blue[0] ;
assign TMDSp_clock = pixelClock;

assign TMDSn[2] 		= !TMDSp[2];
assign TMDSn[1] 		= !TMDSp[1];
assign TMDSn[0] 		= !TMDSp[0];
assign TMDSn_clock	= !TMDSp_clock;

always @(posedge videoInClock)
begin
	// HSync Detector
	sync1<=sync2;
	sync2<=sync3;
	sync3<=videoInData;

	// sync4 0b1FVH1234&nbsp; (1234Protection)
	// H=0 Begin of Video
	// H=1 End Of Video
	if ( (sync1==8'b11111111) && (sync2==8'b00000000) && (sync3==8'b00000000) && ((videoInData&8'b10010000)==8'b10000000) )
	begin
		// Bu clock ile adigimiz son data icerisinde HSYNC isareti var
		// Yani bir sonraki data Cb ile baslayacak, adres 0 olacak ...
		regAddress<=10'b0;
		regChromaSample<=1'b1;
		regHSync<=1'b1;
		
		// Vertical Sync Durumunu Kontrol Et ...
		if ((videoInData&8'b00100000)==8'b00100000)
		begin
			regVSync<=1'b1;
		end else
		begin
			regVSync<=1'b0;
		end
		
	end else
	begin
		if (regChromaSample==0) regAddress<=regAddress+1;
		regChromaSample<=!regChromaSample;
		regHSync<=1'b0;
	end

end

module YCbCr2RGB 
(	
	output reg [7:0]oRed,
	output reg [7:0]oGreen,
	output reg [7:0]oBlue,
	input [7:0]iY,
	input [7:0]iCb,
	input [7:0]iCr,
	input iCLK
);

// TEMP RGB 21Bit+Sign
wire signed	[22:0] mR;
wire signed	[22:0] mG;
wire signed	[22:0] mB;

// -----------------------------------------------------------
// Bu magnitude toplamları maximum 21Bit+Sign olabilir !!!
// -----------------------------------------------------------
// Y*(4096) 			8Bit+12Bit=20Bit+Sign
// 1.772*Cb*(4096)	8Bit+12Bit=20Bit+Sign	
// -----------------------------------------------------------
// R = 1*Y + 1.402*(Cr-128)
// G = 1*Y - 0.344*(cb-128) - 0.714*(cR-128)
// B = 1*Y + 1.772*(Cb-128)
// -----------------------------------------------------------

assign mR =  (iY*4096 + 4096*(iCr-128) + 1647*(iCr-128))>>12; 
assign mG =  (iY*4096 - 1409*(iCb-128) - 2925*(iCr-128))>>12;
assign mB =  (iY*4096 + 4096*(iCb-128) + 3162*(iCb-128))>>12; 

always @(posedge iCLK) 
begin
	oRed&nbsp; [7:0]<=(mR[10])?0:((mR>8'hff)?8'hFF:mR[7:0]);
	oGreen[7:0]<=(mG[10])?0:((mG>8'hff)?8'hFF:mG[7:0]);
	oBlue [7:0]<=(mB[10])?0:((mB>8'hff)?8'hFF:mB[7:0]);
end

endmodule

// ----------------------------------------------------------------------------
// HDMI64 - C64 Video HDMI Converter (with Scanline Effect)
// [url]www.commodore.gen.tr[/url] - delimawi'2016
// ----------------------------------------------------------------------------
// Project based on HDMI Sample Code from fpga4fun.com
// ----------------------------------------------------------------------------

module HDMI_Encoder
(
	input pixelClock,						// 27MHz Incomming Video Pixel Clock
	input pixelClockX10,					// 270MHz HDMI Bit Clock (pixelClockx10)
	input extHSync,
	input extVSync,
	
	output [2:0] TMDSp, TMDSn,			// HDMI Output Pins 
	output TMDSp_clock, TMDSn_clock,
	
	// FIFO Output
	output [9:0] PixelAddress,
	input  [7:0] PixelLuma,
	input  [7:0] PixelChroma,
);

// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------

`define DISPLAY_WIDTH			720
`define DISPLAY_HEIGHT			480
`define FULL_WIDTH				858
`define FULL_HEIGHT				525 //525
`define H_FRONT_PORCH			16
`define H_SYNC						62 
`define V_FRONT_PORCH			9
`define V_SYNC 					6

`define H_SYNC_BEGIN				`DISPLAY_WIDTH+`H_FRONT_PORCH			
`define H_SYNC_END				`H_SYNC_BEGIN+`H_SYNC					
`define V_SYNC_BEGIN				`DISPLAY_HEIGHT+`V_FRONT_PORCH		
`define V_SYNC_END				`V_SYNC_BEGIN+`V_SYNC					

reg [9:0] regXPos, regYPos;			// 10 Bit X,Y Counters (0-1023)
reg regHSync,regVSync,regDrawing;	// HDMI Synch Pulses

reg [7:0]	regRed, regBlue, regGreen;

assign PixelAddress=regXPos;

always @(posedge pixelClock)
begin
	regDrawing<=(regXPos<`DISPLAY_WIDTH)&&(regYPos<`DISPLAY_HEIGHT);
	regHSync <= (regXPos>=`H_SYNC_BEGIN)&&(regXPos<`H_SYNC_END);
	regVSync <= (regYPos>=`V_SYNC_BEGIN) && (regYPos<`V_SYNC_END);
end

reg regExtHSync, regExtVSync;


always @(posedge pixelClock)
begin
	regExtHSync<=extHSync;
	regExtVSync<=extVSync;
	
	// Dusey Senkronu yakaladığın anda degerleri sıfırla 
	if ((extVSync==0) && (regExtVSync==1))
	begin
		regXPos<=0;
		regYPos<=0;
	end else
	begin
		if (regXPos==(`FULL_WIDTH-1))
		begin
			if (regYPos==(`FULL_HEIGHT-1))
			begin
				regYPos<=0;
			end else 
			begin
				regYPos<=regYPos+1'b1;
			end
			regXPos<=0;
		end else
		begin
			regXPos<=regXPos+1'b1;
		end
	end
	
end

// ----------------------------------------------------------------------------
// Scanline Effect & YCbCr > RGB
// ----------------------------------------------------------------------------

reg [7:0] regCr;
reg [7:0] regCb;
	
wire [7:0]	regInpRed, regInpBlue, regInpGreen;

YCbCr2RGB Convert( .oRed(regInpRed), .oGreen(regInpBlue), .oBlue(regInpGreen), .iY(PixelLuma[7:0]), .iCb(regCb), .iCr(regCr), .iCLK(pixelClock));

always @(posedge pixelClock)
begin
	if (regXPos[0]==1)
	begin
		regCr<=PixelChroma;
	end else
	begin
		regCb<=PixelChroma;
	end
	
	if (regYPos[0]==1)
	begin	
		regRed <= (regInpRed>>1);
		regGreen <= (regInpGreen>>1);
		regBlue <= (regInpBlue>>1);
	end
	else
	begin
		regRed 	<= regInpRed;
		regGreen	<= regInpGreen;
		regBlue 	<= regInpBlue;
	end
	
end


// ----------------------------------------------------------------------------
// Generate TDMS Encoded 10 Bit Signals
// ----------------------------------------------------------------------------

wire [9:0] TMDS_red;
wire [9:0] TMDS_green;
wire [9:0] TMDS_blue;

TMDS_encoder encode_R( .clk(pixelClock), .VD(regRed&nbsp; ), .CD(2'b00)&nbsp; &nbsp; &nbsp; &nbsp; , .VDE(regDrawing), .TMDS(TMDS_red)&nbsp; &nbsp; );
TMDS_encoder encode_G( .clk(pixelClock), .VD(regGreen), .CD(2'b00)&nbsp; &nbsp; &nbsp; &nbsp; , .VDE(regDrawing), .TMDS(TMDS_green)&nbsp; );
TMDS_encoder encode_B( .clk(pixelClock), .VD(regBlue ), .CD({regVSync,regHSync}), .VDE(regDrawing), .TMDS(TMDS_blue)&nbsp; &nbsp;);

// ----------------------------------------------------------------------------
// Generate TDMS Clock
// ----------------------------------------------------------------------------

wire clk_TMDS=pixelClockX10;

// ----------------------------------------------------------------------------
// Generate TDMS Signals (Serialise)
// ----------------------------------------------------------------------------

reg [3:0] TMDS_mod10=0;&nbsp; 			// modulus 10 counter
reg [9:0] TMDS_shift_red=0;		// 10 Bit Shift Registers
reg [9:0] TMDS_shift_green=0;		// 10 Bit Shift Registers
reg [9:0] TMDS_shift_blue=0;		// 10 Bit Shift Registers

reg TMDS_shift_load=0;

always @(posedge clk_TMDS) 	TMDS_shift_load <= (TMDS_mod10==4'd9);

always @(posedge clk_TMDS)
begin
	TMDS_shift_red&nbsp; 	<= TMDS_shift_load ? TMDS_red&nbsp; &nbsp;: TMDS_shift_red&nbsp; [9:1];
	TMDS_shift_green	<= TMDS_shift_load ? TMDS_green : TMDS_shift_green[9:1];
	TMDS_shift_blue 	<= TMDS_shift_load ? TMDS_blue&nbsp; : TMDS_shift_blue [9:1];	
	
	TMDS_mod10			<= (TMDS_mod10==4'd9) ? 4'd0 : TMDS_mod10+4'd1;
end

assign TMDSp[2]&nbsp; &nbsp; = TMDS_shift_red[0]&nbsp; ;
assign TMDSp[1]&nbsp; &nbsp; = TMDS_shift_green[0];
assign TMDSp[0]&nbsp; &nbsp; = TMDS_shift_blue[0] ;
assign TMDSp_clock = pixelClock;

assign TMDSn[2] 		= !TMDSp[2];
assign TMDSn[1] 		= !TMDSp[1];
assign TMDSn[0] 		= !TMDSp[0];
assign TMDSn_clock	= !TMDSp_clock;

endmodule

// ----------------------------------------------
// Timing 720x576 @50 Hz
// pixelClock 30MHz
// ---------------------------------------------- 
`define DISPLAY_WIDTH			720
`define DISPLAY_HEIGHT			576
`define FULL_WIDTH				864
`define FULL_HEIGHT				624

`define H_FRONT_PORCH			12
`define H_SYNC						64
 
`define V_FRONT_PORCH			5
`define V_SYNC 					5

// TEMP RGB 21Bit+Sign
wire signed	[22:0] mR;
wire signed	[22:0] mG;
wire signed	[22:0] mB;

// -----------------------------------------------------------
// Bu magnitude toplamları maximum 21Bit+Sign olabilir !!!
// -----------------------------------------------------------
// Y*(4096) 			8Bit+12Bit=20Bit+Sign
// 1.772*Cb*(4096)	8Bit+12Bit=20Bit+Sign	
// -----------------------------------------------------------
// R = 1*Y + 1.402*(Cr-128)
// G = 1*Y - 0.344*(cb-128) - 0.714*(cR-128)
// B = 1*Y + 1.772*(Cb-128)
// -----------------------------------------------------------

assign mR =  (iY*4096 + 4096*(iCr-128) + 1647*(iCr-128))>>12; 
assign mG =  (iY*4096 - 1409*(iCb-128) - 2925*(iCr-128))>>12;
assign mB =  (iY*4096 + 4096*(iCb-128) + 3162*(iCb-128))>>12; 

always @(posedge iCLK) 
begin
	oRed  [7:0]<=(mR[10])?0:((mR>8'hff)?8'hFF:mR[7:0]);
	oGreen[7:0]<=(mG[10])?0:((mG>8'hff)?8'hFF:mG[7:0]);
	oBlue [7:0]<=(mB[10])?0:((mB>8'hff)?8'hFF:mB[7:0]);
end

endmodule